This invention relates to the field of semiconductor processing. More particularly, this invention relates to a method for forming a shallow junction for an integrated circuit.
As lateral integrated circuit device geometries continue to shrink, it often is desirable to commensurately shrink certain vertical geometries of the integrated circuits as well. As the vertical geometries shrink, or in other words as the various layers and structures become thinner, it tends to become increasingly important to control the processes by which the layers and structures are formed. This is because there tends to be less tolerance to variation in the thickness of a relatively thinner structure than there is to variation in the thickness of a relatively thicker structure.
For example, when fabricating integrated circuits such as complimentary metal oxide semiconductors, it is typically desirable to form the source and the drain regions with shallow junction depths in the semiconductor substrate. An oxide layer of from about one hundred angstroms to about two hundred angstroms in thickness is typically deposited over the surface of the semiconductor substrate at some point prior to the implant that forms the junctions, to protect the semiconductor substrate from damage during the implant. The sources and drains are commonly formed by implanting a dopant such as boron or arsenic, depending on the type of junction being formed. These species are typically implanted at an energy of about one thousand electron volts. At this energy, the dopants have a projected total implant depth of a few hundred angstroms. Thus, the thickness of the protective oxide layer plays a very significant part in determining the junction depth for sources and drains formed by the implant.
However, there are other design goals that compete with the design goal of maintaining a uniform and known thickness of the protective oxide layer. For example, a polysilicon gate electrode reoxidation process is typically conducted immediately after the polysilicon gate electrode is etched. The reoxidation process is primarily designed to grow oxide sidewalls on the vertical faces of the polysilicon gate electrode, to protect the polysilicon gate electrode during subsequent processing. Unfortunately, the reoxidation process tends to also grow additional oxide at the interface between the semiconductor substrate and the protective oxide layer, thus increasing the thickness of the protective oxide layer by some amount. The additional thickness of the protective oxide layer effects the depth to which the dopant for the source and drain regions is implanted into the semiconductor substrate, as explained above.
Thus, there is a need for a method of forming junctions in a semiconductor substrate, where the thickness of the protective layer overlying the semiconductor substrate does not increase during the reoxidation of the gate electrode layer.
The above and other needs are met by a method of forming junctions in a semiconductor substrate, where a gate dielectric layer is deposited on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces.
The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer. The impregnation is accomplished using a process that does not impregnate a significant amount of the first species in the exposed vertical faces of the gate electrode. The impregnated sacrificial layer, the exposed vertical faces of the gate electrode, and the impregnated exposed portions of the gate dielectric layer are exposed to an oxidizing environment, causing oxide growth on at least the exposed vertical faces of the gate electrode, and thereby covering the vertical faces of the gate electrode with oxide sidewalls. However, the oxidizing environment does not cause significant oxide growth under the impregnated sacrificial layer and the impregnated exposed portions of the gate dielectric layer.
A second species is impregnated through the impregnated exposed portions of the gate dielectric layer into portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer. The impregnated second species forms junctions in the portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer.
Thus, in this manner junctions with very controlled junction depths are formed in the semiconductor substrate. Because the gate dielectric layer is impregnated with the first species that inhibits diffusion of oxygen, the gate dielectric layer does not appreciably grow in thickness during the oxidation process by which the sidewalls on the gate electrode layer are formed. By maintaining the gate dielectric layer at a known thickness, the results of the process by which the second species is impregnated into the semiconductor substrate are more repeatable, and the junctions can be formed to a finely controlled depth within the semiconductor substrate.
In various preferred embodiments of the invention the semiconductor substrate is monocrystalline silicon, the gate dielectric layer is silicon oxide, the gate electrode layer is polysilicon, and the sacrificial layer is silicon oxide. Most preferably the first species is nitrogen that is impregnated to a concentration of between about three atomic percent and about twenty atomic percent. Also in the preferred embodiment, the impregnated exposed portions of the gate dielectric layer are cleaned prior to the step of impregnating the second species.